10GHz Station Upgrades

With the 2015 September 10GHz and up contest approaching fast, I am in process of making some performance improvements to my 10GHz station. I had already missed the first round of the August 10GHz and up, so I wanted to make sure to complete a few necessary items before the 2nd round is here.

First on the agenda is to upgrade my PLL frequency synth that runs my LO to use low-noise regulators. This was a design error on my part, when I originally designed these freq synths, they had less than ideal phase noise as a result. The noise itself was determined to be coming from the 78nn series of linear regulators I had originally spec'd out for the design for the 5v vco, and dual 3.3v analog and digital supplies. A test of an unused synth I had built (for a beacon project) proved to show quite an impressive improvement once I replaced the regulators:

ADF4107 Phase Noise

Phase noise is shown here on the left with the original noise regulators, and a much cleaner output is shown on the right after the low-noise regulator replacement.

Next item on my list was to add some additional attenuation into the LO path that drives the mixers. Originally when I had a phased lock PLL brick, LO drive power through both outputs was approximately 12dBm. This was ideal for the two Magnum Microwave mixers I was using. After switching to the PLL synth and x4 multiplier, my output to the LO's through a splitter was a little hot at 15dBm. This was the upper max limit of power in the datasheet. This as a result was causing some additional spurs on the RF side, which while immediately filtered was still resulting in some spur leakage. A 3dB pad in line with the output of the x4 multiplier cleaned the excessive spurs up nicely.

The final improvement is in regards to the actual frequency reference itself for the LO PLL freq synth. I had designed my synth to use an on board TCXO protected by a shielded enclosure for both rf shielding and hopefully help stabilize the temperature. Temperature drift is critical in any design, this one was particularly touchy to temperature. When the synth was running and locked to my 2556GHz output frequency, simply blowing air across the TCXO caused the output frequency to start drifting. The specs for the particular crystal I had chosen were not that great at ±2.5ppm over the specified temperature range, I would definitely need to do better for good stability.

I have a rubidium 10MHz reference I use at my bench. I didn't want to devote this just for my mobile station as I use the reference for all of my test equipment. I would also need to frequency double it to work with my ADF4107 PLL as it requires a minimum 20MHz reference. As a compromise, I decided to go with a crystal oven oscillator (OCXO). I had a 20MHz version available that runs off of 12V which will be perfect for this mobile 10GHz station. Details of this will probably be in a separate post due to the difference being pretty interesting.

Decreasing Phase Noise with Low Noise Regulators

I have posted several times in the past on the PLL frequency synthesizer I designed and built based on the Analog Devices ADF4107. The overall design is a platform for a fractional PLL frequency synthesizer for any frequency range up to about 5GHz.  A single frequency or range could be generated simply by changing out the VCO and loop filter and reprogramming the ADF4107s registers. The design overall has worked very well, I have used it as a LO for a 1.42GHz hydrogen line radio telescope, a 2556GHz LO for my 10GHz ham station, and a 5.4GHz LO for some specific satellite downlinks.

One element of the design that has been less than ideal was the devices phase noise. My specific PLL was on average about 10dB to 20dB under spec of what the documented phase noise should be for similar designs using the ADF4107 and Z-Comm VCOs. After reading to the application notes some more and a recommendation via twitter from Tony (KC6QHP) who suggested looking into using very low noise regulators for the design, I decided to make the change.

Searching regulator semiconductor manufacturers for very low noise versions is not an easy task, often, the noise levels are not available in any parametric search. So to keep things simple, I just went with the ADP150 which is what Analog Devices recommends for their own designs including the ADF4107. Now this is definitely something I should have considered to begin with in the design, but it was my fault for not reading the docs and assuming the basic ST Micro KFNN regulators which I often use would be suitable for a project like this. Looking at the datasheets, the stated noise levels of each are quite a bit apart:

KF33:

OUTPUT NOISE  10 Hz to 100 KHz 50 µV rms

ADP150:

OUTPUT NOISE  10 Hz to 100 KHz  9µV rms

The issue I now have is I had designed the board for standard DPAK package regulators, the ADP150 used tiny TSOT packages. Because of this I would have to be creative in mounting the devices in the DPAK footprints. This turned out to not be too bad of a task although not the most elegant solution.

The results speak for themselves, after replacing the regulators with the ADP150s, phase noise has considerably decreased. I have already started on a version 2 of this synthesizer and I will be definitely switching to these regulators for all future versions.

Standard KF33 and 7805 regulators on the left, low noise ADP150 regulators on the right.

Analog Devices ADF4107 Based RF Frequency Synthesizer

I have had a few projects recently needing a stable local oscillator (LO) source for downconversion, notably my hydrogen line radio telescope and a few receivers for low earth orbit high frequency satellite transmitting in the 5.8Ghz range. I have attempted the use of various VCOs along with a very stable power supply to produce a stable LO frequency, but this over the long term has proven unsuccessful. My previous designs used a  precision adjustable voltage regulator trying both analog and digital precision trim-pots, but temperature drift among other things resulted with it being too difficult to keep a stable frequency. These solutions would need constant calibration which proved to be unreliable for a true stable LO source. An alternate good solution could be the use of a precision frequency synthesizer / phase-locked loop from a reference source to produce a stable frequency. Researching frequency synthesizers, I came across the Analog Devices ADF series of PLL frequency synthesizers which I ultimately ended up choosing for my design.

I wanted the design to be flexible, that is with a single board I could populate it with a variety of VCOs only having to update the ADF4107 register configuration and the loop filter component values to produce a fixed or tunable frequency. My final design achieved this goal.

ADF4107 based frequency synthesizer

This design was based on the Analog Devices ADF4107 frequency synthesizer. The ADF4107 consists of a low-noise phase frequency detector that uses a programmable reference divider and prescaler to run a VCO via a precision charge pump to produce a stable locked frequency from a fixed reference oscillator. There are many variations within the ADF frequency synth family, I chose the 4107 as it met my needs with a maximum frequency of 7Ghz.

The ADF4107 can utilize a variety of VCOs, I chose to go with a Z-Comm device which I have used in many previous designs. The specific VCO used in this version is a V940ME02. It has an adjustable output frequency range of 5220 to 5420Mhz which fit well into the 5.40Ghz LO needed for my downconverter. The reference input to the PLL is provided by a 32Mhz TCXO crystal, which was a last minute change as I ordered the wrong package type for the original 20Mhz TCXO I had specified for the design. Only some reference counter changes were needed to use the alternate crystal that I had in my parts bin.

The ADF4107 itself is a very complex device looking at both its usage and programming. To help integrate this family into your design, Analog Devices has a great tool called ADIsimPLL to assist with the initial design regarding calculations of output frequency range based on the reference frequency input. It will also assist with selecting the loop filter component values based on a given design among many other useful things.

ADIsimPLL screenshot

My ADF4107 synthesizer is controlled via a SPI bus from a Microchip PIC18F14K50 microcontroller. After the initial power up of the ADF4107, multiple registers must be sequentially loaded to define the prescaler counters among other configuration flags. The PIC stores and handles this configuration. I have also included an external serial interface into the design to allow remote tuning and control of the frequency synthesizer via the PIC, although in this specific design it is not being used as it only needs to provide a single hard-coded fixed frequency.

The design itself follows good mixed-signal design practices. The board is a four-layer design that I had received from my favorite fab house, OSH Park. Upon receiving, I populated by first board by hand and had a working board on power up. ADF4107 register programming took a bit as the specific loading order of the registers was tricky, but once mastered, the PLL immediately locked onto 5.40Ghz according to my frequency counter. I couldn't view it directly on my spectrum analyzer as it only goes to 3Ghz, but the frequency counter was nicely stable at 5.4 Ghz plus or minus a few hundred hz. Each subsequent PLL lock is almost instantaneous. I added two LEDs to some spare PIC outputs, one of them is used to indicate when there is PLL lock and a spare that can be used for any additional status I wish to see.

An output filter is included in the design, in this case it has a center frequency of 5.4Ghz. Filters of this frequency are easy to find as they are used a lot in 802.11a WLAN hardware. I did not include an output amplifier on this board as I had planned to keep the design as simple as possible, instead I would be using an external amplifier. This will need to be the case as the output of this VCO at 5.4Ghz is -15dBm, which is not high enough to provide a LO for most mixers. So on any future redesigns, I may add an amplifier back in.