One element of the design that has been less than ideal was the devices phase noise. My specific PLL was on average about 10dB to 20dB under spec of what the documented phase noise should be for similar designs using the ADF4107 and Z-Comm VCOs. After reading to the application notes some more and a recommendation via twitter from Tony (KC6QHP) who suggested looking into using very low noise regulators for the design, I decided to make the change.
Searching regulator semiconductor manufacturers for very low noise versions is not an easy task, often, the noise levels are not available in any parametric search. So to keep things simple, I just went with the ADP150 which is what Analog Devices recommends for their own designs including the ADF4107. Now this is definitely something I should have considered to begin with in the design, but it was my fault for not reading the docs and assuming the basic ST Micro KFNN regulators which I often use would be suitable for a project like this. Looking at the datasheets, the stated noise levels of each are quite a bit apart:
OUTPUT NOISE 10 Hz to 100 KHz 50 µV rms
OUTPUT NOISE 10 Hz to 100 KHz 9µV rms
The issue I now have is I had designed the board for standard DPAK package regulators, the ADP150 used tiny TSOT packages. Because of this I would have to be creative in mounting the devices in the DPAK footprints. This turned out to not be too bad of a task although not the most elegant solution.
The results speak for themselves, after replacing the regulators with the ADP150s, phase noise has considerably decreased. I have already started on a version 2 of this synthesizer and I will be definitely switching to these regulators for all future versions.
|Standard KF33 and 7805 regulators on the left, low noise ADP150 regulators on the right.|