Showing posts with label CPLD. Show all posts
Showing posts with label CPLD. Show all posts

Monday, June 11, 2012

Altera EPM3256A CPLD Breakout

A few months ago I received my newly designed breakout boards from Laen's OSH Park PCB service and finally had time to assemble my new boards. Stepping up from my original EPM3032A board I went to the EPM3256A here in its final assembled form:




With this new board I only broke out about 100 or so pins of the 208 pin package, this will be more than enough for the projects I have planned with it. I added a few features to it including an on-board socketed crystal with options for 3.3v or 5v operation. I also have options to route the clock to the global clock input or a specified general purpose io pin depending on the application.

A couple nice features about the MAX3000 series specifically to the EPM3256A:

- 3.3v and 5v compatibility. Makes interfacing existing logic very easy.
- 256 macrocells available. Small compared to modern FPGAs, but is enough to be very useful.
- 158 Usable i/o pins.

I will be posting some projects based on this board very soon.

Friday, November 18, 2011

ALTERA EPM3032A CPLD Breakout Board

Recently I came across a large quantity of NetApp DS14 Filers that were being disposed of which are basically Fiber Channel shelves full of FC drives. While a few of these ended up in my basement 48U rack for FC attached storage, the rest I scavenged as many parts from as possible. These shelves have removable modules depending on the interfaces required. On these modules two parts caught my eye:



Two ALTERA CPLDs from the Max 3000 family. An EPM3256A and an EPM3032A. While I was excited about both devices, the EPM3032A I was initially more excited for as it is a more manageable package size.

After removing about 10 or so of these CPLDs from the boards I went ahead and designed a simple breakout board in Eagle. All 44 pins are broken out and I included an onboard 3.3V regulator along with a JTAG connector. Upon receiving the boards I threw one together, wrote a simple 4 bit counter in VHDL in Quartus II and downloaded to the CPLD via JTAG to see it worked perfectly.



The EPM3032A is not a large CPLD, with only 32 macrocells it's by no means a device for large scale logic implementations. The 4 bit counter ended up using 4 macrocells or 13% of the usable space in the CPLD, but it is perfect when you need a small custom logic device where many individual chips would be required. I'll be working on a breakout for the more powerful EPM3256A soon.